Single Crystal Silicon Wafer Manufacturing

The silicon wafers so familiar to those of us in the semiconductor industry are actually thin slices of a large single crystal of silicon that was grown from melted electronic grade polycrystalline silicon. The process used in growing these single crystals is known as the Czochralski process after its inventor, Jan Czochralski. Figure 1 shows the basic sequence and components involved in the Czochralski process.

The Czochralski process is carried out in an evacuable chamber, commonly referred to as a “crystal puller” that holds a large crucible, usually quartz, and an electric heating element (Figure 1(a)). Semiconductor grade polysilicon is loaded (charged) into the crucible along with precise amounts of any dopants such as phosphorus or boron that may be needed to give the product wafers specified P or N characteristics. Evacuation removes any air from the chamber to avoid oxidation of the heated silicon during the growth process. The charged crucible is electrically heated to a temperature sufficient to melt the polysilicon (greater than 1421ºC). Once the silicon charge is fully melted, a small seed crystal, mounted on a rod, is lowered into the molten silicon. The seed crystal is typically about 5 mm in diameter and up to 300 mm long. It acts as a “starter” for the growth of the larger silicon crystal from the melt. The seed crystal is mounted on the rod with a known crystal facet vertically oriented in the melt (crystal facets are defined by “Miller Indices”). In the case of seed crystals, facets having Miller indices of <100>, <110> or <111> are typically chosen. The crystal growth from the melt will conform to this initial orientation, giving the final large single crystal a known crystal orientation. Following immersion in the melt, the seed crystal is slowly (a few cm/hour) pulled from the melt as the larger crystal grows. The pull speed determines the final diameter of the large crystal. Both the crystal and the crucible are rotated during a crystal pull to improve the homogeneity of the crystal and dopant distribution. The final large crystal is cylindrical in shape; it is called a “boule.” Czochralski growth is the most economical method for the production of silicon crystal boules suitable for producing silicon wafers for general semiconductor device fabrication (known as CZ wafers). The method can form boules large enough to produce silicon wafers up to 450 mm in diameter. However, the method has certain limitations. Since the boule is grown in a quartz (SiO₂) crucible, some oxygen contamination is always present in the silicon (typically 1018 atoms cm-3 or 20 ppm). Graphite crucibles have been used to avoid this contamination, however they produce carbon impurities in the silicon, albeit at an order of magnitude lower in concentration. Both oxygen and carbon impurities lower the minority carrier diffusion length in the final silicon wafer. Dopant homogeneity in the axial and radial directions is also limited in Czochralski silicon, making it difficult to obtain wafers with resistivities greater than 100 ohm-cm.

Higher purity silicon can be produced by a method known as Float Zone (FZ) refining. In this method, a polycrystalline silicon ingot is mounted vertically in the growth chamber, either under vacuum or inert atmosphere. The ingot is not in contact with any of the chamber components except for the ambient gas and a seed crystal of known orientation at its base (Figure 2). The ingot is heated using non-contact radio-frequency (RF) coils that establish a zone of melted material in the ingot, typically about 2 cm thick. In the FZ process, the rod moves vertically downward, allowing the molten zone to move up the length of the ingot, pushing impurities ahead of the melt and leaving behind highly purified single crystal silicon. FZ silicon wafers have resistivities as high as 10,000 ohm-cm.

Once the silicon boule has been created, it is cut into manageable lengths and each length ground to the desired diameter. Orientation flats that indicate the silicon doping and orientation for wafers of less than 200 mm diameter are also ground into the boule at this stage. For wafers with diameters less than 200 mm, the primary (largest) flat is oriented perpendicular to a specified crystal axis such as <111> or <100> (see Figure 3). Secondary (smaller) flats indicate whether a wafer is either p-type or n-type. 200 mm (8-inch) and 300 mm (12-inch) wafers use a single notch oriented to the specified crystal axis to indicate wafer orientation with no indicator for doping type. Figure 3 shows the relationship between wafer type and the placement of flats on the wafer edge.

After the boule has been ground to the desired diameter and the flats have been created, it is cut into thin slices using either a diamond encrusted blade or a steel wire. The edges of the silicon slices are usually rounded at this stage. Laser markings designating silicon type, resistivity, manufacturer, etc. are also added near the primary flat at this time. Both surfaces of the unfinished slice are ground and lapped  to bring all of the slices to within a specified thickness and flatness tolerance. Grinding brings the slice into a rough thickness and flatness tolerance after which the lapping process removes the last bit of unwanted material from the slice faces, leaving a smooth, flat, unpolished surface. Lapping typically achieves tolerances of less than 2.5 µm uniformity in wafer surface flatness.

The final stage in silicon wafer manufacture involves chemically etching away any surface layers that may have accumulated crystal damage and contamination during sawing, grinding and lapping; followed by chemical mechanical polishing (CMP) to produce a highly reflective, scratch and damage free surface on one side of the wafer. The chemical etch is accomplished using an etchant solution of hydrofluoric acid (HF) mixed with nitric and acetic acids that can dissolve silicon. In CMP, silicon slices are mounted onto a carrier and placed in a CMP machine where they undergo combined chemical and mechanical polishing. Typically, CMP employs a hard polyurethane polishing pad combined with a slurry of finely dispersed alumina or silica abrasive particles in an alkaline solution. The finished product of the CMP process is the silicon wafer that we, as users, are familiar with. It has a highly reflective, scratch and damage free surface on one side on which semiconductor devices can be fabricated.